期刊名称：International Journal of Computer Networks & Communications
印刷版ISSN：0975-2293
电子版ISSN：0974-9322
出版年度：2010
卷号：2
期号：4
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor’s power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.
