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  • 标题:FTL Based carry look ahead adder design using floating gates
  • 本地全文:下载
  • 作者:P.H.S.T. Murthy ; K. Chaitanya ; Malleswara Rao.V
  • 期刊名称:International Journal of Computer Science & Technology
  • 印刷版ISSN:2229-4333
  • 电子版ISSN:0976-8491
  • 出版年度:2011
  • 卷号:2
  • 期号:2(Version 2)
  • 出版社:Ayushmaan Technologies
  • 摘要:Low-voltage and low-power circuit structures are substantive for almost all mobile electronic gadgets which generally have mixed mode circuit structures embedded with analog sub-sections. Using the reconfigurable logic of multi-input floating gate MOSFETs, 4-bit full adder has been designed for 1.1V operation. Multi-input floating gate (MIFG) transistors have been anticipating in realizing the increased functionality on a chip. A multi-input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. Implementing a design using multiinput floating gate MOSFETs brings down transistor count and number of interconnections. Here in this we have presented how to eliminate the propagate and generate signals This tends the design to become more efficient in area and power consumption by using feed through logic. The following information is about Carry look ahead adder circuit, tested with 45nm technology and is extended to ALU. The proposed circuit has been implemented in 45n-well CMOS technology. But the problem with above circuitry is power consumption. Power consumption can be reduced drastically by dynamic circuits but still ftl improves the speed of operation because it’s rail to rail voltage is in between the 0.5v-1v.In this project carry look ahead adder is implemented with ftl which propagation delay is 96ps.
  • 关键词:Mirror adder circuit; MIFG; FTL; CMOS adder.n
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