期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2011
卷号：2
期号：4Ver 3
出版社：Ayushmaan Technologies
摘要：This article presents an optimal placement method in order to sizing and sitting of capacitor banks in IEEE 33 bus test system. The algorithm for optimization in this paper is Simulated Annealing (SA). The proposed objective function considers active power losses of the system and the voltage profile in nominal load of system. In order to use of simulated annealing algorithm, at first, placement problem is written as an optimization problem which includes the objective function and constraints, and then to achieve the most desirable results, simulated annealing method is applied to solve the problem. High performance of the proposed algorithm in mention system is verified by simulations in MATLAB software and in order to illustrate of feasibility of proposed method this optimization in three cases–one capacitor bank, two capacitor banks, and three capacitor banks will accomplish.
