期刊名称：International Journal of Computer Science and Communication Networks
电子版ISSN：2249-5789
出版年度：2012
卷号：2
期号：3
页码：307-309
出版社：Technopark Publications
摘要：A new leading-zero anticipatory (LZA) logic for high-speed floating-point addition and subtraction is proposed. The pre-decoding for normalization concurrently with addition for the significant is carried out in this logic. Shift operation of normalization in parallel with the rounding operation is also performed. The use of simple Boolean algebra allows the proposed logic to be constructed from a simple CMOS circuit
