期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2010
卷号：1
期号：1
页码：24-32
出版社：TechScience Publications
摘要：High performance computing systems can be designed using parallel processing. The effectiveness of these parallel systems rests primarily on the communication network linking processors and memory modules. Hence, an interconnection network that provides the desired connectivity and performance at minimum cost is required. The design of a suitable interconnection network for inter-processor communication is one of the key issues of the system performance. In this paper a new multistage interconnection network IASEN (Irregular augmented shuffle exchange) has been proposed modifying existing ASEN-2 network. ASEN-2 is a regular multipath network with limited fault tolerance. The paper also discusses the permutation possibility behavior of both the networks with and without faults. It has been observed that the proposed multistage interconnection network IASEN provides much better fault-tolerance by providing more paths between any pair of source-destination as compared to ASEN-2 at the expanse of little more cost.
