期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2010
卷号：1
期号：5
页码：337-341
出版社：TechScience Publications
摘要：This paper presents a methodology to reduce the area of DSP architecture on silicon using folding. Folding is particularly important and has impact on large DSP circuits/architectures. This technique is powerful to reduce functional units in DSP circuits/architectures which mainly depend on folding factor. The folding technique is used to derive the control circuitry of the hardware architectures such as functional units (adders and multipliers). Folding technique also supports complex operations with time multiplexing. The time multiplexing reduces the area by repeating computations on the same hardware unit. Apart from folding technique, register minimization technique is used to minimize the number of registers. This methodology is verified using Spartan 3A/3AN device family. The comparison table of unfolded and folded circuits shows the better performance of the folding algorithm.
