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  • 标题:Design and Implementation of Pipelined 32-bit Advanced RISC Processor for Various D.S.P Applications
  • 本地全文:下载
  • 作者:J.Poornima ; G.V.Ganesh ; M.jyothi
  • 期刊名称:International Journal of Computer Science and Information Technologies
  • 电子版ISSN:0975-9646
  • 出版年度:2012
  • 卷号:3
  • 期号:1
  • 页码:3208-3213
  • 出版社:TechScience Publications
  • 摘要:In this paper, we propose 32-bit pipelined RISC processor using VLIW architectures. This processor is especially used for both D.S.P applications and general purpose applications. Reduced instruction is the main criteria used to develop in this processor. With a single instruction scheme, more executions can be done using S.I.M.E. processor consists of the blocks namely program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incrementer circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. In this paper, we have extended the utility of the processor towards convolution and correlation applications, which are the most important digital signal processing applications
  • 关键词:RISC; VLIW; SIME; Convolution;Correlation.SOPs
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