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  • 标题:A Low Power Area Efficient Design for 1-bit Full Adder Cell
  • 本地全文:下载
  • 作者:Manoj Kumar R ; Krishna Murthy M
  • 期刊名称:International Journal of Computer Science and Information Technologies
  • 电子版ISSN:0975-9646
  • 出版年度:2012
  • 卷号:3
  • 期号:3
  • 页码:4139-4142
  • 出版社:TechScience Publications
  • 摘要:In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area was measured using Micro Wind Tool.
  • 关键词:Majority Function; Area ; Power Consumption....
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