期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2013
卷号：4
期号：3
页码：423-425
出版社：TechScience Publications
摘要：This paper proposes novel low power full adder cell to be used as Shannon adder in the Neural Network applications. By using the Shannon’s theorem the gate count is reduced thereby the total chip area gets minimized. Hence the power also gets reduced to a considerable amount. The designs are implemented using TANNER tool which results in significant reduction in area & power for the Modified Shannon based full adder cell when compared with MCIT based full adder cell.
