期刊名称：International Journal on Electrical Engineering and Informatics
印刷版ISSN：2085-6830
出版年度：2011
卷号：3
期号：2
出版社：School of Electrical Engineering and Informatics
摘要：The purpose of this paper is to design a prevented glitch circuit (PGC) to avoid the destroyed that is caused to glitch in the paralleling comparator Flash ADC. The advantages of this prevented glitch circuit are high-speed, lower power consumption, and size effective, furthermore, it also reduce the faults. We used the TSPC’s D flip-flop to achieve this prevented glitch circuit where reduces and improves the glitches and faults, respectively. The PGC is simulated by the Tanner Pro. 13.0 with Generic0_25μm techniques in 0.25-μm. Summarizing the features of this implemented circuit is lower power of 3.3V at 333.3MHz, higher area density is 89.6%, and lower area size is 1221.16×721.793μm2.
