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  • 标题:Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures
  • 本地全文:下载
  • 作者:Umamaheswari S ; Rajapaul Perinbam J
  • 期刊名称:International Journal of Distributed and Parallel Systems
  • 印刷版ISSN:2229-3957
  • 电子版ISSN:0976-9757
  • 出版年度:2011
  • 卷号:2
  • 期号:5
  • DOI:10.5121/ijdps.2011.2504
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:Network-on-chip has been proposed in System-on-Chip to achieve high performance, reusability and scalability through generating application specific topologies. Application specific topologies are irregular in structure and take into account certain factors like communication weight, area and energy constraints while building up the topology. Regular topologies like 2D mesh, spidergon are more structured and are built not considering much about the system characteristics and other requirements. Consequently the throughput, power utilization and silicon area vary depending on the topology. This paper provides an evaluation of the performance measures of the regular topological structures and irregular application specific NoC.
  • 关键词:Network on Chip (NoC); Irregular topology; performance comparison; Topology generation;Throughput; Energy; silicon area.
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