期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2011
卷号：8
期号：4
出版社：IJCSI Press
摘要：Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters, routing nodes, and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. The area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.
关键词：Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters; routing nodes; and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. The area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.
