期刊名称：International Journal on Computer Science and Engineering
印刷版ISSN：2229-5631
电子版ISSN：0975-3397
出版年度：2011
卷号：3
期号：4
页码：1713-1720
出版社：Engg Journals Publications
摘要：Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. Partial Reconfigurable FPGAs allow tasks to be placed and removed dynamically at runtime. These reconfigurable systems have a 2-layer hardware and software architecture that permits a variety of different interfaces. Further, these systems enable self-reconfiguration under software control through a reconfiguration hardware interface called Internal Configuration Access Port (ICAP). In this paper, experiments are conducted in order to evaluate the design complexity and reconfiguration latency of self reconfiguration. The results show that the main goal of self reconfiguration is to shorten the reconfiguration time while not degrading the performance of the final design.
