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  • 标题:Modeling Of Combinational Circuits Based On Ternary Multiplexer Using VHDL
  • 本地全文:下载
  • 作者:A.Sathish kumar ; A.Swetha Priya
  • 期刊名称:International Journal on Computer Science and Engineering
  • 印刷版ISSN:2229-5631
  • 电子版ISSN:0975-3397
  • 出版年度:2010
  • 卷号:2
  • 期号:5
  • 页码:1777-1791
  • 出版社:Engg Journals Publications
  • 摘要:This paper presents a novel method for defining, analyzing, testing and implementing the basic combinational circuitry with VHDL Simulator. This paper shows the potential of VHDL modeling and simulation that can be applied to Ternary switching circuits to verify its functionality and timing specifications. A novel method is brought out for implementing the basic combinational circuitry with minimum number of multiplexers. It also includes 1-bit and 2-bit position shifter and Barrel shifter. Method of coding is illustrated with respect to block diagram. An intention is to show how proposed simulator can be used to simulate MVL circuits and to evaluate system performance.
  • 关键词:MVL; 9-state logic system; Reliability-Unreliability model; VHDL
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