期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2013
卷号：2
期号：2
页码：582-588
出版社：Buldanshahr : IJECSE
摘要：A 2-D discrete wavelet transform hardware design based on multiplier design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The multiplier design based technique has been applied to reduce the number of delay. This paper provides the clearcut idea in about the application of 8-multiplier and 6-adder in one, two & three level of architecture This architecture is suitable for high speed on-line applications, the most important one being image processing, reduced the area and power in the discrete wavelet transform. With this architecture the speed of the 2-D discrete wavelet transform is increased. It has 100% hardware utilization efficiency.
关键词：2-D Discrete wavelet transform (DWT); one level multiplier based design; two level multiplier;based design; three level multiplier based design; multiplier based design scheme; Xilinx simulation.
