标题：A Duly Synchronized, Straightforward Approach For Realizing the General Characteristics of JK Flip – Flop and Master – Slave JK Flip – Flop in terms of Characteristic Equation of Clocked SR Latch
期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2013
卷号：2
期号：2
页码：817-822
出版社：Buldanshahr : IJECSE
摘要：In this paper we propose a duly synchronized, straightforward approach for realizing the general characteristics of JK flip – flop and master – slave JK flip – flop in terms of the characteristic equation of clocked SR latch. Although, in this connection, the traditional approach requires exercising all possible external input combinations one by one on concerned logic diagrams until acquiring stable states; the proposed approach does not require the same. Also, it duly treats clocked SR latch as the basic 1 – bit cell of static RAM. The proposed approach is more efficient than the traditional approach, not only as a tool of analysis and design of complex sequential circuits; but also as a tool of teaching.
关键词：Duly synchronized; Straightforward approach; JK flip – flop; Master – Slave JK flip – flop; SR latch;Stable State; Static RAM; Complex sequential circuit
