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  • 标题:Design of a Floating-Point Fused Add-Subtract Unit Using Verilog
  • 本地全文:下载
  • 作者:Mayank Sharma ; Prince Nagar ; Ghanshyam Kumar Singh
  • 期刊名称:International Journal of Electronics and Computer Science Engineering
  • 电子版ISSN:2277-1956
  • 出版年度:2013
  • 卷号:2
  • 期号:3
  • 页码:1007-1013
  • 出版社:Buldanshahr : IJECSE
  • 摘要:A floating-point (FP) fused add-subtract unit is presented that performs simultaneous floating-point operation of add-subtract on a common pair of single-precision data at the same time that it takes to perform in a single addition with a conventional floating-point adder. The system was placed and routed in 45nm process so that there will be less consumption of memory as well as power.
  • 关键词:Floating-point adder (FPA); Fused add-subtractor (FAS); Verilog
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