期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2013
卷号：2
期号：3
页码：1018-1025
出版社：Buldanshahr : IJECSE
摘要：In this paper VHDL implementation of complex number multiplier using ancient Vedic mathematics and conventional modified Booth algorithm is presented and compared. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay. The simulation results for 4 bit multiplication using Booth’s algorithm and using Vedic sutra are illustrated.
