期刊名称：International Journal of Multimedia and Ubiquitous Engineering
印刷版ISSN：1975-0080
出版年度：2013
卷号：8
期号：1
出版社：SERSC
摘要：Integer Discrete Cosine Transform (DCT) is among the techniques used to improve the performance of the H.264/AVC Standard. All the profiles in the H.264/AVC standard support 4×4 integer DCT and the high profiles of this standard support 8×8 integer DCT as well as the 4×4 integer DCT. Various hardware realizations have been proposed for forward and inverse integer DCT in the literature because they are among the computational intensive units in the H.264/AVC standard. In this paper we propose a unified pipelined architecture to realize of the entire forward and inverse DCTs as well as the Hadamard transforms in the H.264/AVC encoder. The synthesis results indicate that our architecture achieves higher clock rate and relatively lower gate count compared to the other published architectures that realize only a number of the transforms in the H.264/AVC encoder.
