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  • 标题:Stagnant Timing investigation of Embedded Software on Advanced Processor ArchitecturesA Classifier Ensemble of Binary Classifier Ensembles
  • 本地全文:下载
  • 作者:M.Shankar ; M.Sridar ; M.Rajani
  • 期刊名称:International Journal of Electronics Communication and Computer Technology
  • 印刷版ISSN:2249-7838
  • 出版年度:2012
  • 卷号:2
  • 期号:1
  • 页码:36
  • 出版社:International Journal of Electronics Communication and Computer Technology
  • 摘要:Most processors today are embedded in products like mobile phones, microwave owns, welding machines etc and are not used in PC's as many believe Since some of these embedded computers are used in time-critical or safety-critical systems it is very important that the behaviour of these systems are well known. One part of that is to know the Worst Case Execution Time (WCET) of the different tasks in the embedded system. First, shortcomings in current as w ell as future standards to controlling the power grid are outlined. From these economic and safety threats, we derive an immediate need to invest in research on the protection of the power grid, both from the perspective of cyber attacks and distributed control system problems. Seco nd, current software design practice does not adequately verify and validate worst-case timing scenarios that have to be guaranteed in order to meet deadlines in safety-critical embedded systems. This equally applies to avionics and the auto motive industry, both of which are increasingly requiring their suppliers to provide v ariable bounds on worst-case execution time of software
  • 关键词:Architecture; Execution Times; visualization; ;threads.
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