期刊名称：International Journal of Electronics Communication and Computer Technology
印刷版ISSN：2249-7838
出版年度：2012
卷号：2
期号：4
页码：155
出版社：International Journal of Electronics Communication and Computer Technology
摘要：We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for w ireless receiver system. The LNA is fabricated with the 0.18 μm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for the design of Differential Low Noise A mplifier. Consuming 9mA current at 1.8V supply voltage, the proposed LNA exhibits a power gain of 15.87 dB, noise Figure (NF) of 2.4 dB, S11 of -9.842 dB and S12 of -42.86dB.The input IP3 (IIP3) at 2 GHz is -2.86127dBm, and consumes 16.2 mW of power
