期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2013
卷号：3
期号：5
出版社：S.S. Mishra
摘要：A new circuit technique is proposed in this literature to simultaneously reduce sub-threshold leakage as well as gate-oxide leakage power consumption at high and low temperatures in footed domino logic circuits in ultra-deep submicron technology, as gate leakage is dominant for ultra thin gate insulating layer (i.e. tox > 20.). Here we are using the dual threshold voltage technique to reduce the leakage current as well as propagation delay and sleep switches to further reduce leakage current. At 110oC, proposed Circuit I & proposed Circuit II work improves 34%-70% as compared to multiple-Vt with low and high inputs. At room temperatures, proposed work improves 20%-57% as compared to multiple-Vt with low and high inputs.
