期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2013
卷号：3
期号：4
出版社：S.S. Mishra
摘要：SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high performance processors. A SRAM cell must meet the requirements for the operation in submicron/nano ranges. The scaling of CMOS technology has significant impacts on SRAM cell ¨C random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the SRAM cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve. In this paper we compared different type of SRAM topology, at a 180nm CMOS technology to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. Cadence Virtuoso simulation in standard 180nm CMOS technology confirms all results obtained from this paper.
关键词：Conventional SRAM; nT SRAM; Low Power; Leakage Current; Output waveform
