期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：5
出版社：S.S. Mishra
摘要：Floating point adders a re h ard to implement on recon figurable hardware because floating poin t addition is the most compl ex operation since the align ment of manti ssa i s required before manti ssa addition . Vari ous parameters are outlined such as clock period, combi national delay, chi p area i.e . nu mber of slices, clock speed e tc. when we impleme nt fl oating point adde r on recon figurable hardware . Implementation of floating point adder on diffe rent FPGAs cause s change i n consu mption of chi p are a on u sing diffe rent reconfigu rabl e hardware. Impleme ntati on of fl oatin g point adder on Virte x 4 cons umes only 7% a chip are a i.e. consu mes 401 s lices out of 5472 slices with a offset delay of 27.891n sec while implemen tation of floatin g poi nt adder on S partan 2 consu mes 52% of ch ip area cause s a offset delay of 79.378nse c an d the gre atest utiliz ation of chip area i s required while u sing Virtex 2 for th e impleme ntati on it utiliz es 155% of ch ip area.
关键词：Floatin g point adder; FPG As; Combinational delay; Chip area; Xilin x
