期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：5
出版社：S.S. Mishra
摘要：Addition is one of the fundamental arithmetic operations, which is used extensively in many VLSI systems such as application-specific DSP architectures and microprocessors. The adders determine the overall performance of the circuits in most of those systems. This paper introduces a novel low power and high-speed 8-Transistor 1-bit full adder cell, which is proposed. In this design, a novel low power and high speed 8-Transistor 1-bit full adder cell have six MOS transistors and multiplexer using two MOS transistors are applied to minimize the transistor count and reduce the power consumption and delay. The power dissipation and delay of the new design against other designs are analyzed via HSPICE simulations. The results feature that the proposed adder has both lower power consumption and high-speed operation. The combination of low power and low transistor count makes the new 8T full adder cell a viable option for an efficient design
