期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：6
出版社：S.S. Mishra
摘要：Static power dissipation is increases with the scaling in threshold voltage and expected to become important part of total power consumption. In the present work, a new configuration of level shifters for low power application in 0.25¦Ìm technology has been presented. The proposed circuits utilize the merit of stacking technique by which there is reduction in leakage power. In this work a new level-up shifter designed at ultra low core voltage and has wide range of I/O voltage. The circuit is designed using 0.25¦Ìm CMOS process. Proposed level shifter uses stacking technique to reduce static power dissipation with a little addition in area. Less static power dissipation allow level shifter suitability for wide I/O interface voltage applications in CMOS Technology with very little power dissipation
关键词：CMOS; Static Power Dissipation; Level Shifter Threshold voltage; Ultra Low Core Voltage and Stacking Technique
