期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：11
出版社：S.S. Mishra
摘要：For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. We propose a novel approach named master slave tri-state buffer with control logic which reduces the total power & delay of elastic buffer. The paper presents a design and implementation of tri-state buffer mechanism. This design offers also the advantage of third state (High Impedance state) of tri -state buffer. The proposed elastic buffer design using tri-state buffer is implemented in Cadence tools. The obtained result shows that our design is effective in terms 20.50 % reduction in total power, 89.67% reduction in delay.
