期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：4
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：A two stage CMOS power amplifier is implemented in 0.13¦Ìm RF CMOS technology using ADS tool operating at 2.4 GHz with dc supply of 2.5 V. Driver stage as the input stage and power stage as the output stage are the two stages. A cascode topology is used in the driver stage and basic topology is used in the power stage. Output power at 1dB compression point is 20.028 dBm and maximum output power delivered by this circuit is 22.002 dBm. Power added efficiency calculated at 1 dB compression point is 44.669 % whereas the maximum power added efficiency comes out to be 70.196 %. The input return and output return losses are -11.132 dB and -12.467 dB respectively. Isolation loss and small signal gain are calculated to be -61.889 dB and 43.745 dB respectively. This circuit shows power gain of 42.728 dB at 1dB compression point. The total dc current flowing through this circuit is 0.0901 A. MOSFET only bias circuits are used to reduce total dc current. This circuit is designed for application in WLAN.
