摘要：Register file access time represents one of the critical delays of currentmicroprocessors, and it is expected to become more critical as future processors increasethe instruction window size and the issue width. This paper present a novel dynamicregister renaming scheme that delays the allocation of physical registers until a late stagein the pipeline. We show that it can provide important savings in number of physicalregisters so it can significantly shorter the register file access time. Delaying the allocationof physical registers requires some artifact to keep track of dependences. This is achievedby introducing the concept of virtual-physical registers, which are tags that do not requireany storage location. The proposed renaming scheme shortens the average number of cyclesthat each physical register is allocated, and allows for an early execution of instructionssince they can obtain a physical register for its destination earlier than with theconventional scheme. Early execution is especially beneficial for branches and memoryoperations, since the former can be resolved earlier and the latter can prefetch their data inadvance
