摘要：DRAM row-bu.ers have become a critical level of cache in the memory hierarchyto exploit spatial locality in the cache miss stream. Row-bu.er con.icts occur whena sequence of requests on di.erent pages goes to the same memory bank, causinghigher memory access latency than requests to the same row or to di.erent banks.In this study, we first show that the address mapping symmetry between the cacheand DRAM is the inherent source of row-bu.er con.icts. Breaking the symmetryto reduce the con.icts and to retain the spatial locality, we propose and evaluate apermutation-based page interleaving scheme. We have also evaluated and comparedtwo representative cache mapping schemes that break the symmetry at the cache level.We show that the proposed page interleaving scheme outperforms all other mappingschemes based on its overall performance and on its implementation simplicity.
