摘要：Cache memories have been incorporated into almost all modern, general-purpose microprocessors. Tomaintain data consistency between cache structures and the rest of the memory systems, most ofthese caches employ either a writeback or a write-through strategy to deal with store operations. Write-through caches propagate data to more distant memory levels at the time each store occurs, producing asignificant bus tra.c overhead to maintain consistency between the memory hierarchy levels. Writebackcaches can significantly reduce the bandwidth requirements between caches and memory by markingcache lines as dirty when stores are processed and writing those lines to the memory system only whenthat dirty line is evicted. Writeback caches work well for many applications; however, for applicationsthat experience significant numbers of cache misses over a very short interval due to streaming data,writeback cache designs can degrade overall system performance by clustering bus activity when dirtylines contend with data being fetched into the cache.In this paper we present a technique called Eager Writeback, which avoids performance loss dueto clustered memory tra.c patterns found in streaming and graphics applications by speculatively"cleaning" dirty cache lines prior to their eviction. Eager Writeback can be viewed as a compromisebetween write-through and writeback policies, in which dirty lines are written later than write-through,but prior to writeback. We will show that this approach can e.ectively avoid the performance degrada-tion caused by clustering bus tra.c in a writeback approach, while incurring very minimal additionalmemory tra.c
