摘要：Clustering is an approach that many microprocessors are adopting in recent times in order to mitigatethe increasing penalties of wire delays. In this work we propose a novel clustered VLIW architecture whichhas all its resources partitioned among clusters, including the cache memory. A modulo scheduling schemefor this architecture is also proposed. This algorithm takes into account both register and memory inter-clus-ter communications so that the final schedule results in a cluster assignment that favors cluster locality incache references and register accesses. It has been evaluated for both 2- and 4-cluster configurations and fordiffering number and latencies of inter-cluster buses. The proposed algorithm produces schedules with verylow communication requirements and outperforms previous cluster-oriented schedulers
