摘要：As microprocessor designs continue to evolve, many optimizations reach a point of diminish-ing returns. We introduce HLS, a hybrid processor simulator which uses statistical models andsymbolic execution to evaluate design alternatives. This simulation methodology enables quickand accurate generation of contour maps of the performance space spanned by design parameters.We validate the accuracy of HLS through correlation with existing cycle-by-cycle simulation tech-niques and current generation hardware. We demonstrate the power of HLS by exploring designspaces defined by two parameters: code properties and value prediction. These examples motivatehow HLS can be used to set design goals and individual component performance targets
