摘要：The trend towards larger structures and aggressive clock frequencies has been a fundamentaldriving force for modern microprocessor design. While one approach is to deeply pipeline anyhigh delay structure, dependencies and critical loops have made it increasingly difficult to speedexecution through extensive pipelining. One alternative is to remove larger structures from the crit-ical path. We explore the ramifications of stripping all but the most necessary functionality out ofthe processing core, leaving only a tiny.-core. Although past studies have shown the possibilityto build decoupled structures for some individual helper structures, the impact of streamlining allof these structures at the same time has not been explored. Along with describing the challengesin decoupling the helper engines, we focus on the performance, power consumption and thermalbehavior of the.-core architecture. We use a detailed performance, power and thermal modeling inour analysis. Our results indicate that the.-core provides a 20% reduction in power over a conven-tional monolithic core, while providing comparable performance (1% improvement on average).By dynamically configuring the helper engines to different application phases, an additional 13%power savings can be attained with only an average 3% degradation in performance. Our experimental analysis also show that the microcore architecture has favorable thermal behavior, with 86%fewer thermally-critical cycles compared to a monolithic core
