期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2012
卷号：1
期号：2
页码：173-180
出版社：Buldanshahr : IJECSE
摘要：Speed of digital arithmetic processor depends mainly on the speed of adders. This paper provides a technique so that we can increase the speed of addition. Hybrid signed digit number representation perform addition in such a way that the carry propagation chain is limited to single digit position and hence are used to speed up arithmetic operation. Also hybrid signed digit reduces the critical path delay by parallelizing. Hybrid signed digit can be appropriate to use, when output is redundant representation
