期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2012
卷号：1
期号：2
页码：497-501
出版社：Buldanshahr : IJECSE
摘要：Floating point operations are hard to implement on FPGAs because of complexity of their algorithm. On the other hand many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point adder in both the concurrent and sequential processing module have been explored. For the processing module various parameters i.e. speed, clock period, chip area (no. of slices used), modeling format, combinational delay, total number of destination paths will be compared. Comparing various parameters will provide with the information that which type of processing in a floating point adder will take more clock period and less chip area for same given input
