期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2012
卷号：1
期号：2
页码：520-526
出版社：Buldanshahr : IJECSE
摘要：To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing clock speed is not viable due to heat dissipation and power consumption constraints. Hence Instead of trying to increase the clock speed, multi-core processor architectures with the lower frequency can be used. A multi-core processor is a single integrated circuit in which two or more processors have been attached for enhanced performance, reduced power consumption and more efficient simultaneous processing of multiple tasks. Multi-core processors, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance. Well scheduling of running threads on these processors will result in achieving higher performance. Modern multi-core systems are designed to allow clusters of cores to share various hardware structures, such as last-level caches, memory controllers, and interconnections without considering these shared resources, scheduling the threads will cause serious degradation in overall performance of the system. In this paper we are showing one basic problem in multicore processor. The simulation results showed that the requirement of scheduler or cache-controller to avoid lot of problems that come in to the existence during shared caches memory shared by many cores located on single chip as well as the simple solution on it with simulation result
