期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2012
卷号：1
期号：2
页码：751-756
出版社：Buldanshahr : IJECSE
摘要：Low-Density Parity-Check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. These codes offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often imple mented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional Hardware Description Language (HDL) based approach is a complex and time consuming task. In this paper HDL Implementation of Low Density Parity Check Decoder architecture is presented with different rates i.e. 1/2, 2/3, 3/4, 4/7, 8/9, 9/10 and variable data lengths i.e. 8, 16, 32, 64, 128, 256 bits and consequent changeable precision factor
