期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2012
卷号：1
期号：3
页码：1163-1166
出版社：Buldanshahr : IJECSE
摘要：This paper presents the pipeline architecture of high-speed modified booth multipliers. The proposed multiplier circuits are based on the modified booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. The proposed multiplier operate at high ranges, so, they can be used in the systems requiring very high performance. In VLSI, the multiplication of quadratic and cubic functions are becoming difficult with present algorithms. So, we prefer a function known as 'Pipelined Quadratic Function'. This function operates based on polynomial equation. By using this function, we can implement the multiplication process with less additions and subtractions
