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  • 标题:VLSI Design of a 16-bit Pipelined RISC Processor
  • 本地全文:下载
  • 作者:Tannu Chhabra ; Md Tauheed Khan
  • 期刊名称:International Journal of Electronics and Computer Science Engineering
  • 电子版ISSN:2277-1956
  • 出版年度:2012
  • 卷号:1
  • 期号:3
  • 页码:1858-1861
  • 出版社:Buldanshahr : IJECSE
  • 摘要:In this paper we have described the design of a 16-bit pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor has been designed to be implemented on an FPGA using VHDL such that one can reconfigure it according to specific requirements of the target applications. The processor is powerful enough to be used as a stand-alone processing element and is generic enough to be used in multi-processor System on Chip
  • 关键词:RISC processor; Pipelining; VLSI; FPGA; Computer Architecture; Real-time embedded systems; System on Chip ;(SoC)
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