The cost for testing integrated circuits and systems is growing rapidly as their complexity is increasing as per Moore?s law. Cost modeling plays a very vital role in reducing test cost and time to market. It also gives estimate of overall testing. The economics modeling for VLSI testing with Automatic Test Equipment (ATE) is presented in this paper. The mathematical relations are developed for cost model to test the VLSI circuits based on the parameters of ATE testing, further cost modeling equations are modeled into Graphical User Interface(GUI) in Matlab, which can be used as a cost estimation tool . A case study is done for Set-top-box, Microprocessor, Device A to verify the functionality of the developed estimation tool. It helps the Test engineers for estimating the testing cost for the test planning.