期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：5
DOI：10.5121/vlsic.2013.4501
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper proposes a validation method for the design of a CPU on which, in parallel with the development of the CPU, it is also manually described a testbench that performs automated testing on the instructions that are being described. The testbench consists of the original program memory of the CPU and it is also coupled to the internal registers, PORTS, stack and other components related to the project. The program memory sends the instructions requested by the processor and checks the results of its instructions, progressing or not with the tests. The proposed method resulted in a CPU compatible with the instruction set and the CPU registers present into the PIC16F628 microcontroller. In order to shows the usability and success of the depuration method employed, this work shows that the CPU developed is capable of running real programs generated by compilers existing on the market. The proposed CPU was mapped in FPGA, and using Cadence tools, was synthesized on silicon
