期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：5
DOI：10.5121/vlsic.2013.4508
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：The design of an ultra low voltage, low power high speed 8 channel Analog multiplexer in 180nm CMOS technology is presented. A modified transmission gate using a dynamic threshold voltage MOSFET (DTMOS) is employed in the design. The design is optimized with respect to critical requirements like short switching time, low power dissipation, good linearity and high dynamic range with an operating voltage of 0.4V. The ON and OFF resistances achieved are 32 ohms and 10Mohms respectively with a switching speed of 10MHz. The power dissipation obtained is around 2.65uW for a dynamic range of 1uV to 0.4V
关键词：Analog multiplexer; low power; high speed; body-bias
