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  • 标题:BPNN Based Power Estimation of Sequential Circuits
  • 本地全文:下载
  • 作者:S.Arun Kavi Arasu ; Fiona.E.Josy ; N.Manibharathi
  • 期刊名称:International Journal of Advanced Research In Computer Science and Software Engineering
  • 印刷版ISSN:2277-6451
  • 电子版ISSN:2277-128X
  • 出版年度:2013
  • 卷号:3
  • 期号:11
  • 出版社:S.S. Mishra
  • 摘要:Early Power estimation is important in VLSI circuits, because it has a significant impact on the reliability of these circuits. Power estimation is a tradeoff between precision and estimation time. Simulation based power estimation techniques are time consuming. This work reports an artificial neural network based method for power estimation of ISCAS'89 Benchmark circuits, by employing back propagation algorithm (BPNN). This method can estimate power quickly and precisely from I/O and gate info rmation of the VLSI circuit, without requiring detailed structure of the circuit and its interconnection. Power estimation results reported in the literature for 20 ISCAS' 89 Benchmark circuits were used to the train the neural network. The trained netwo rk is tested on 5 circuits left out during the training process. The results of the tested circuits were validated by performing regression analysis. The BPNN was trained with training functions namely Traingdx and Traingdm
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