期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2013
卷号：3
期号：8
出版社：S.S. Mishra
摘要：In nanoscale CMOS technologies, SRAMs employ aggressively small cells, which make them extremely vulnerable to process variations, degrading the write-ability of SRAM. The increased effect of process variations in nanoscale technologies requires additional techniques and treatments such as write assist techniques to ensure fast and reliable write operation. Many write assist techniques e.g. reduce VDDat cell, raise VSSat cell, WL(word- line) boost, strengthen pass gate NMOS, weaken pull-up PMOS, negative bit-line scheme have been presented earlier, out of which negative bit line voltage scheme and WL (word- line) boost scheme have been found two most promising solutio ns for assisting write operation of SRAM. Negative voltage required for negative bit-line voltage scheme is generated on chip. A major drawback of negative-bit line voltage scheme is that due to negative spike generated, reliability of circuit degrades. A new low power write assist scheme is presented in this paper in which negative bit-line voltage scheme is combined with WL(word line) boost technique to increase the reliability and performance of the write assist circuit
