期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2013
卷号：3
期号：8
出版社：S.S. Mishra
摘要：As the technology is moving towards the lower Nano regimes, due to scaling the read and write margins in SRAM are decreasing sharply and may lead to operation failure. So it becomes mandatory to use SRAM Assist circuits in these regimes. In this paper new NBLV assist circuits are presented which gives better margins as compared to conventional SRAM Assist circuits. The proposed circuit utilizes the merit of negative bit line voltage and negative Vss techniques for write and read assistance respectively. This circuit is designed in 250nm CMOS technology. Increased write and read margins makes these circuits more robust, stable and fast.
关键词：CMO S; NBLV; Write margins and Read margins; Process Variation; Readability
