期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2013
卷号：3
期号：8
出版社：S.S. Mishra
摘要：Low power is a challenging work in digital design .In digital circuits, a shift register or a counter is a cascade of flip flops, and also they form a sequential logic. Implementing power o ptimizatio n o n all the components of the shift registers i s a choice. S h if t r eg i st ers co m p ri se s one of the m o s t b a si c o p era ti o na l unit in any p rocessor and m ultip liers to process the output of the systems. This paper mainly concentrates on power reduction of the digital components by introducing a novel architecture. This proposed architecture eliminates the conducting path in between voltage rail to ground rail during state transitions by providing high resistance path, so that the short circuit current in between rails can be reduced which in turn causes drastically reduction in power consumption. These different circuit parameters are evaluated with TANNER 13.1 using IBM SCN CMOS 250nm technology at room temperature. The simulation results indicate that the proposed architecture has reduced 40% of power dissipation when compared with that of conventional Architectures.
