期刊名称：International Journal of Computer Technology and Applications
电子版ISSN：2229-6093
出版年度：2011
卷号：2
期号：6
页码：1964-1969
出版社：Technopark Publications
摘要：Cryptographic pairing (bilinear mapping) is a core algorithm for various cryptography protocols. It is computationally expensive and inefficiently computed with general purpose processors. Although there has been previous work looking into efficient hardware designs for pairing, most of these systems use small characteristic curves which are incompatible with practical software designs. In this paper, we propose novel processor architecture for pairing-based cryptography applications using large characteristic curves. It takes advantage of some unique FPGA features such as huge aggregated memory bandwidth and massively parallel computation logic to achieve high performance and high energy efficiency. The proposed architecture is ideal for server-side applications requiring flexibility, performance and energy efficiency
关键词：Finite Field Arithmetic Unit; Weil Pairing; Multi Precision Arithmetic; Pairing Processor
