Designing thermal-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density. Extremely high power density, thus the very high onchip temperature, not only significantly increases the packaging and cooling cost, but also creates tremendous difficulties in chip leakage control and reliability. As a major contributor to chip transistor budget and die area, caches account for a significant share of the overall processor power consumption, including both dynamic and leakage power. This work proposes to characterize the thermal behavior within data caches at the fine granularity instead of treating the data cache as a monolithic block. It develops detailed thermal models for a typical subarrayed data cache. Furthermore, this work proposes and evaluates a new subarray scheme, namely way-interleaved scheme, to improve the thermal behavior of subarrays. This optimized cache microarchitecture can be also combined with dynamic thermal management techniques to further improve the efficiency of the thermal management. The interaction between leakage control and thermal optimization is also investigated in the context of thermal-aware microarchitectural designs.