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  • 标题:A super-polynomial lower bound for regular arithmetic formulas.
  • 本地全文:下载
  • 作者:Neeraj Kayal ; Chandan Saha ; Ramprasad Saptharishi
  • 期刊名称:Electronic Colloquium on Computational Complexity
  • 印刷版ISSN:1433-8092
  • 出版年度:2013
  • 卷号:2013
  • 出版社:Universität Trier, Lehrstuhl für Theoretische Computer-Forschung
  • 摘要:

    We consider arithmetic formulas consisting of alternating layers of addition (+) and multiplication () gates such that the fanin of all the gates in any fixed layer is the same. Such a formula which additionally has the property that its formal/syntactic degree is at most twice the (total) degree of its output polynomial, we refer to as a regular formula. As usual, we allow arbitrary constants from the underlying field F on the incoming edges to a + gate so that a + gate can in fact compute an arbitrary F-linear combination of its inputs. We show that there is an (n2+1)-variate polynomial of degree 2n in VNP such that any regular formula computing it must be of size at least n(logn).

    Along the way, we examine depth four () regular formulas wherein all multiplication gates in the layer adjacent to the inputs have fanin a and all multiplication gates in the layer adjacent to the output node have fanin b. We refer to such formulas as [b][a]-formulas. We show that there exists an n2-variate polynomial of degree n in VNP such that any [O(n)][n] -formula computing it must have top fan-in at least 2(nlogn) . In comparison, Tavenas (MFCS 2013) has recently shown that every nO(1)-variate polynomial of degree n in VP admits a [O(n)][n] -formula of top fan-in 2O(nlogn) . This means that any further asymptotic improvement either in our lower bound for such formulas (to say 2(nlogn) ) or in Tavenas' upper bound (to say 2o(nlogn) ) will imply that VP is different from VNP.

  • 关键词:arithmetic formulas; depth-4 circuits; lower bounds; VNP; VP
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